Field programmable gate arrays (FPGAs) have experienced an exponential growth in the past thirty years. When FPGAs were first debuted in the mid- to late-eighties, an FPGA chip had less than 100 lookup tables (LUTs) and it was used as simple glue logic. Today, the logic gate equivalent capacity of a commercial FPGA chip reaches tens of millions gates. A median size application specific integrated circuit (ASIC) could be mapped into a single FPGA chip. Along with the ever-increasing capacity, FPGA architecture has also evolved. A large number of macro blocks such as memories, processors, high-speed inputs/outputs and clock synchronization circuitry are hard-wired within FPGA chips. This expands the range of applications that can be implemented in a single device. Moreover, FPGA chips can operate at speeds of hundreds of megahertz, close to an average ASIC clock rate. The above factors have resulted in the growth in popularity of FPGA prototyping.
An FPGA-based prototype allows hardware designers to develop and test their systems. Implementation errors and basic conceptual bugs are usually caught early in the verification process using simulation and emulation techniques. FPGA prototyping is typically deployed near the end of the verification process to catch system-level issues. For designs that rely heavily on commercial IP, an FPGA-based prototype is an ideal test platform for ensuring all IP components perform together.
An FPGA-based prototype can also serve as a vehicle for software development and validation. Embedded software has become the dominant part of the effort in modern System-on-Chip (SoC) design. FPGA prototyping provides software developers early access to a fully functioning hardware platform well before real silicon. This enables early software development tasks such as operating system (OS) integration and application testing. The increased productivity of software development and validation greatly accelerates a product's time-to-market.
Although the capacity of FPGAs has grown significantly over the years, they have not kept up with non-FPGA-based targeted integrated circuits (e.g., custom integrated circuits and ASICs). Not many modern designs fit in a single FPGA chip. As a result, designs often must be partitioned across multiple FPGA chips. Arbitrary partitioning may require a great deal of interconnect among chips and the resultant system may not perform as expected.
Besides partitioning, synthesis can also affect a prototype's performance. FPGA prototyping is usually performed after simulation-based verification is mostly finished and the register-transfer level (RTL) design is fairly mature. The synthesis process converts the RTL design into an FPGA-mapped netlist, which is then placed and routed in FPGA chip(s). One of the most important reasons to perform prototyping is to achieve the highest possible performance compared with other verification methods such as emulation. Poor synthesis can jeopardize this aim. Various techniques are employed in the synthesis process to meet both space and performance goals by inferring regular structures from a RTL design, optimizing them and efficiently mapping them into FPGA chips.
Mapping a design to FPGA prototype hardware is very time-consuming. As noted previously, the FPGA prototype is a much faster engine for running the RTL design model, but if the effort to setup the model is added, then the speed benefit may soon be eliminated. It is therefore desirable to develop a fast FPGA prototyping setup process without sacrificing the quality of the design implementation.